This invention relates to the packaging of electronic devices, and, more particularly, to the structure upon which integrated circuits and the like are supported for inserting into an electronic circuit assembly.
Integrated circuits are electronic devices that are extremely miniaturized, so that hundreds or even thousands of individual circuits and active elements are formed on a chip that may be only 1/2 inch on a side. The reduction in size of such circuits reduces their weight and volume requirements, and also increases their operating speeds because the distances that electrons must travel are reduced. The widespread adoption of integrated circuitry has revolutionized many areas of electronics.
The integrated circuits themselves are extremely small and fragile. They must therefore be packaged and protected in a manner that permits external electrical connections to be made, and permits the integrated circuits to be handled in a normal manner during the assembly and repair of electronic devices that may utilize one or many such packaged integrated circuits.
One approach to packaging is to attach the integrated circuit to a substrate. The substrate supports the integrated circuit, and provides electrical connection points Fine wires are attached between pads on the integrated circuit and pads on the substrate, and typically electrical conductor paths (termed "traces") extend from the pads on the substrate to other locations on the substrate that are spaced apart sufficiently that external connections can be readily made.
The substrate is normally electrically nonconducting, so that there is a natural insulation barrier between the various conductor traces that run across the surface of the substrate. The mounted integrated circuit is also electrically isolated on its bottom side, and can be electrically isolated on the top side by applying an insulation layer. One popular material of construction of the substrate is an organic resin material that is readily formed and also is nonconducting. These resin boards, known as printed circuit boards, are often found inside commercial and industrial electronic systems such as computers, radios and televisions. Mounting of the integrated circuit on the resin board insulates it electrically from the surroundings on its bottom side, and a layer of liquid resin is often spread over the top of the integrated circuit and allowed to harden, substrate electrically insulate the integrated circuit on the top side.
An alternative approach has been to use a piece of ceramic as a substrate, and to join the conductor traces run across the surface of the substrate to provide external electrical connections. A cover or lid can be attached over the integrated circuit to protect it. Such a package is known as a hermetic package, because it provides an electrically insulating, long-lasting, completely sealed support for the electronic device mounted upon it that is impervious to external substances such as moisture that could damage the integrated circuit. The preparation of hermetic packages presents different, and typically more complex, problems than does the preparation of nonhermetic packages, which are not impervious to moisture, because of restrictions on the materials and techniques of construction. The present invention is applicable to such hermetic packaging for electronic devices.
The following United States Patents, which are incorporated herein by reference, disclose various ceramic packages and techniques for making such packages.
U.S. Pat. No. 4,320,438 discloses a multi-layer ceramic package having a plurality of ceramic lamina each having a conductive pattern and in which there is an internal cavity within which there is a chip or a chip array. The chip or chip array is connected through short wire bonds to the ceramic lamina which have a conductive pattern. The conductive patterns on the various layers are interconnected.
U.S. Pat. No. 4,753,820 discloses a leadless ceramic package in which the bond pads on the pre-fired ceramic which are furthest from the center of the package are wider than those pads closest to the center. The bond pads are deposited by methods well known in the art such as photolithographic deposition.
U.S. Pat. No. 4,761,518 discloses a package in which a semiconductor casing is formed of a ceramic-glass-metal composite material with a lead frame embedded in a base component. The lead frame may include holes to mechanically interlock with the composite material. The patent relates to both ceramic dual-in-line packages (CERDIP) and ceramic four-sided packages (CERAQUAD).
U.S. Pat. No. 4,801,765 discloses a semiconductor package having external contacts to the chip provided by interdigitated leads formed from upper and lower lead frames. The lower lead frame includes a paddle for mounting the chip. The upper lead frame initially has its leads tied together and a center portion is removed by punching to fit the size of the chip.
U.S. Pat. No. 4,874,721 discloses a method of manufacturing a multichip package. The package comprises a ceramic multilayer substrate having a multilayer circuit wiring therein and input/output pins connected to a lower surface of the multilayer substrate. A first vertical wiring is formed on an upper layer of the first polyimide insulating layer. A plurality of semiconductor elements each having a second polyimide insulating layer and a second vertical wiring are connected to the first polyimide insulating layer and the first vertical wiring.
U.S. Pat. No. 4,890,153 discloses a package having a ceramic layer containing an inner row of bonding pads and an outer row of bonding pads. Bonding wires extend from the bonding pads on the VLSI die to the opposing pads on the inner and outer rows to provide an electrical interface between the die and the packages. The inner and outer bonding pads are connected by metallized fingers to conductive pads which provide a power and signal interface.
U.S. Pat. No. 4,906,802 discloses a package having a first molded section having a first predetermined shape and a second molded section having a second predetermined shape. One of the molded sections is made from a non-conductive material and the other is made from a non-conductive material that is capable of receiving a deposit of conductive material. A conductive material is deposited on the outer exposed surface of the molded section capable of receiving the deposit. This particular molded section has an outer surfaces that defines a plurality of non-intersecting, continuous paths that form the input/output leads on the molded chip carrier body. A protective cap can be placed over an electronic chip mounted within the package.
U.S. Pat. No. 4,933,741 discloses that a ground plane for an electrical conductor can comprise a plurality of isolated segments to provide alternate conductors having a lower impedance than the associated plurality of conductors. The segmented ground plane is electrically isolated from and maintained substantially in parallel with the conductors by means of an insulating layer such as polyimide.
U.S. Pat. No. 4,992,628 discloses a package having a glass material selectively deposited on a base substrate to form at least one discrete void or recess for housing an integrated circuit chip. The lead frame having a plurality of leads and the ground plane are both embedded in the glass material that is selectively deposited. The ground plane may be a layer of conductive material physically separated from the die attach pad by the ceramic or glass thus is electrically isolated from the pad. The package utilizes low temperature sealing glass and has reduced lead to lead capacitance.
U.S. Pat. No. 5,012,323 discloses a package incorporating a pair of semiconductor dice on a single lead frame having a wire-bonding region at each end of a die-attachment region which has both an upper and lower surface. The first of the pair of dice is back bonded to the upper surface of the die attachment region and the second is face bonded to the lower surface of the die attachment region. Electrical interconnection between the second die and the lead frame pass through an aperture in the lead frame.
Most of the cost of conventional multilayered packages is incurred in the complex series of steps requires to fabricate the packages. Thus, "cost" is a way of expressing the totality of the technical difficulties in preparing the packages. Conducting channels termed vias can be formed through the ceramic substrate, and the pins can be attached to one side of the vias. Several types of electrically conducting materials can be used in the conducting traces on the top side of the base and connected together ed to end to form series paths. The portion of the trace nearest the integrated circuit is gold to permit attachment substrate aluminum wires extending to the integrated circuit. The portion of the trace adjacent the vias is an alloy of silver and palladium to prevent leaching of the silver into the solder used to connect the two. The intermediate portion of the trace is silver. Each portion of the path must be separately deposited on the substrate. Yields of final, good quality packages are reduced as the number of individual steps increases, simply because there are always some failures in each individual step. The complex structure is also prone to service failures related to the mode of fabrication, such as failures at the joints between the various segments of the top-surface conduction traces or separation of the pins.
For these and other reasons, the cost of multilevel ceramic packages has remained relatively high. It would be desirable to develop a multilayered package that has significantly reduced cost, reflecting a technically less complex method of fabrication, is of simpler construction so as to be more reliable in service, and which can accommodate increasingly smaller sized semiconductors chips. The present invention fulfills this need, and further provides related advantages.
It is believed, therefore, that a ceramic package having a lower cost and which exhibits improved overall performance of the semiconductor devices represents an advancement in the art.